GATE CS - DIGITAL LOGIC:K-maps and Sequential Circuits
Mastering k-maps and sequential circuits concepts and implementation.
K-maps and Sequential Circuits for GATE CS
GATE Digital Logic favourites: K-map minimization (including wrap-around groups) and flip-flop excitation / conversion. Counters and state machines appear as short design or next-state questions.
K-maps
Gray-code axes. Groups of 1,2,4,8… cells; rectangular; wrap edges/corners. Don't-cares may enlarge groups.
4-variable layout (common)
CD=00 CD=01 CD=11 CD=10
AB=00 | m0 | m1 | m3 | m2 |
AB=01 | m4 | m5 | m7 | m6 |
AB=11 | m12 | m13 | m15 | m14 |
AB=10 | m8 | m9 | m11 | m10 |
Trap: missing a wrapped pair of 1s (corners). Always re-check adjacency on the torus.
SOP from 1-groups; POS from 0-groups when asked.
Flip-flops
| FF | Characteristic (Q⁺) |
|---|---|
| SR | Set/reset; 11 forbidden (basic SR) |
| D | Q⁺ = D |
| JK | Toggle when J=K=1 |
| T | Toggle when T=1 |
Excitation tables (needed Q → Q⁺, what inputs?) are the conversion key. GATE: "convert JK to T" → express J,K in terms of T and Q.
Counters / FSM
Synchronous vs asynchronous ripple. Mod-n: how many FFs, when reset. Moore (output = f(state)) vs Mealy (f(state,input)).
Draw the state diagram before writing excitation equations.
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