GATE CS - COMPUTER ORGANIZATION:CPU Design and Pipelining

CPU Design and Pipelining for GATE CS

GATE pipeline questions are numerical: speedup, stalls from hazards, and occasionally forwarding. Draw the stage timeline.

Classic 5-stage sketch

IF → ID → EX → MEM → WB. Ideal speedup approaches number of stages when the pipeline is full and hazard-free.

Speedup (idealized)

Without pipeline: time ≈ $n \times k \times t$ for $n$ instructions, $k$ stages, stage time $t$.

With pipeline (no stalls): ≈ $(k + n - 1) t$.

Speedup ≈ $(n k) / (k + n - 1) \to k$ as $n$ grows.

Hazards

Worked: load-use stall

If EX needs a value loaded in the previous instruction’s MEM, even with forwarding you may need one stall. GATE states whether forwarding exists — read the assumption.

CPI with stalls

$\text{effective CPI} = 1 + \text{stalls per instruction}$ for a single-issue pipeline that would otherwise be CPI 1.

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