CPU Design and Pipelining

CPU Design and Pipelining

The CPU (Central Processing Unit) is the brain of the computer. Understanding CPU design and pipelining is crucial for GATE CS.

CPU Components

1. Arithmetic Logic Unit (ALU)

Performs arithmetic and logical operations.

Operations:

• Addition, subtraction
• AND, OR, XOR, NOT
• Shift operations
• Comparison

Inputs:

• Operand 1 (from register)
• Operand 2 (from register or immediate)
• Operation code (from control unit)

Outputs:

• Result (to register)
• Status flags (zero, carry, overflow, sign)

2. Control Unit

Directs the operation of the processor.

Functions:

• Instruction fetch
• Instruction decode
• Generate control signals
• Coordinate data flow

Types:

• Hardwired Control: Fixed logic circuits
• Microprogrammed Control: Stored microinstructions

3. Registers

Fast storage locations within CPU.

Types:

• General Purpose Registers: For data
• Special Purpose Registers:
• PC (Program Counter): Address of next instruction
• IR (Instruction Register): Current instruction
• MAR (Memory Address Register): Memory address
• MBR (Memory Buffer Register): Data to/from memory
• ACC (Accumulator): For arithmetic operations
• Status Register: Condition codes/flags

Instruction Execution

Single-Cycle Implementation

Each instruction completes in one clock cycle.

Advantages:

• Simple design
• Predictable timing

Disadvantages:

• Clock cycle must accommodate slowest instruction
• Inefficient for simple instructions

Multi-Cycle Implementation

Instructions take multiple cycles.

Advantages:

• Different instructions can take different times
• More efficient

Disadvantages:

• More complex control
• Variable execution time

Pipelining

Pipelining is a technique where multiple instructions are overlapped in execution.

Basic Pipeline Stages

5-Stage Pipeline:

1. IF (Instruction Fetch): Get instruction from memory
2. ID (Instruction Decode): Decode instruction, read registers
3. EX (Execute): Perform ALU operation
4. MEM (Memory Access): Access memory if needed
5. WB (Write Back): Write result to register

Pipeline Performance

Without Pipelining:

• Time per instruction = 5 cycles
• For n instructions: 5n cycles

With Pipelining:

• First instruction: 5 cycles
• Subsequent instructions: 1 cycle each
• For n instructions: 5 + (n-1) cycles

Speedup = 5n / (5 + n - 1) = 5n / (n + 4)

For large n, speedup approaches 5.

Pipeline Hazards

1. Structural Hazards

Occur when hardware resources are insufficient.

Example: Single memory port for both instruction and data fetch.

Solution:

• Separate instruction and data caches
• Multiple memory ports

2. Data Hazards

Occur when instruction depends on result of previous instruction.

Types:

• RAW (Read After Write): True dependency
• WAR (Write After Read): Anti-dependency
• WAW (Write After Write): Output dependency

Example:

ADD R1, R2, R3   ; R1 = R2 + R3
SUB R4, R1, R5   ; R4 = R1 - R5 (depends on R1)

Solutions:

• Forwarding (Bypassing): Forward result directly to next stage
• Pipeline Stalls: Insert bubbles (NOPs)
• Instruction Reordering: Reorder independent instructions

3. Control Hazards

Occur due to branches and jumps.

Problem: Don't know next instruction until branch is resolved.

Solutions:

• Branch Prediction: Predict branch outcome
• Static: Always taken/not taken
• Dynamic: Based on history
• Delayed Branch: Execute instruction after branch
• Branch Target Buffer: Cache branch targets

Pipeline Stalls

When hazard cannot be resolved, pipeline must stall.

Stall = Bubble = NOP

Performance Impact:

• Reduces pipeline efficiency
• Increases CPI (Cycles Per Instruction)

Superscalar Architecture

Executes multiple instructions per cycle.

Features:

• Multiple execution units
• Instruction-level parallelism
• Out-of-order execution

Example: Can execute 2 ADD and 1 MUL simultaneously.

GATE CS Important Points

1. Pipeline Stages: Know 5-stage pipeline thoroughly
2. Hazards: Understand all three types and solutions
3. Forwarding: Know how to resolve data hazards
4. Performance: Calculate speedup and CPI
5. Branch Prediction: Understand prediction techniques

Practice Tips

1. Draw Pipeline Diagrams: Visualize instruction flow
2. Identify Hazards: Practice detecting hazards
3. Calculate Performance: Practice speedup calculations
4. Trace Execution: Manually trace pipelined execution
5. Previous Year Questions: Solve GATE pipelining questions