GATE CS - COMPUTER ORGANIZATION:Instruction Set Architecture
Mastering instruction set architecture concepts and implementation.
Instruction Set Architecture for GATE CS
GATE ISA questions ask addressing modes, instruction format fields, and sometimes endianness or number of memory accesses. Rarely “design an ISA.”
What the ISA fixes
Instruction opcodes, operand types, register file visibility, addressing modes, exception / interrupt model at the programming level.
Addressing modes (know effects)
| Mode | Effective address idea |
|---|---|
| Immediate | Operand in instruction |
| Register | Operand in register |
| Direct / absolute | Address in instruction |
| Register indirect | Address in register |
| Displacement / based | Reg + offset |
| PC-relative | PC + offset (branches) |
| Indexed | Base + index (± scale) |
Trap: counting memory references — immediate needs none for the operand; register indirect needs a memory access for the data.
Formats
Fixed vs variable length. Fields: opcode, regs, immediate/offset. RISC-style: load/store only touch memory; ALU on registers.
Endianness
Big vs little: byte order in a multi-byte word. GATE may give memory contents and ask the integer value.
Next: Pipelining.