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GATE CS - Computer Organization
Master CPU design, instruction formats, pipelining, and memory hierarchy
50 questions•5 pages•~75 min
Use this quiz track to strengthen recall, speed, and exam-style decision making. Attempt one page first, review explanations, and then re-attempt incorrect questions without notes.
A good scoring strategy is to mark uncertain questions, finish known ones quickly, and return with elimination logic. This improves accuracy while keeping momentum under time constraints.
Progress: 0 / 500%
Page 2 of 5 • Questions 11-20 of 50
Q11easy
What is the purpose of TLB (Translation Lookaside Buffer)?
Q12easy
What is the main function of the Control Unit?
Q13medium
What is the time complexity of a 5-stage pipeline for n instructions?
Q14easy
What is a structural hazard in pipelining?
Q15medium
What is the main advantage of write-back cache over write-through?
Q16easy
What is the cache replacement policy that replaces least recently used block?
Q17easy
What is the main purpose of the Instruction Register (IR)?
Q18medium
What is the effective address in register indirect addressing?
Q19medium
What is the main advantage of microprogrammed control over hardwired control?
Q20easy
What is the cache hit ratio if 90% of accesses are hits?
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