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GATE CS - Computer Organization
Master CPU design, instruction formats, pipelining, and memory hierarchy
50 questions•5 pages•~75 min
Use this quiz track to strengthen recall, speed, and exam-style decision making. Attempt one page first, review explanations, and then re-attempt incorrect questions without notes.
A good scoring strategy is to mark uncertain questions, finish known ones quickly, and return with elimination logic. This improves accuracy while keeping momentum under time constraints.
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Page 3 of 5 • Questions 21-30 of 50
Q21easy
What is the main purpose of the Memory Address Register (MAR)?
Q22medium
What is the main disadvantage of direct-mapped cache?
Q23medium
What is the speedup of a 5-stage pipeline for large number of instructions?
Q24medium
What is the main purpose of branch prediction?
Q25easy
What is the cache block size also called?
Q26medium
What is the main advantage of fully associative cache?
Q27medium
What is the main disadvantage of fully associative cache?
Q28easy
What is the purpose of the Memory Buffer Register (MBR)?
Q29medium
What is the main advantage of set-associative cache over fully associative?
Q30medium