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GATE CS - Computer Organization
Master CPU design, instruction formats, pipelining, and memory hierarchy
50 questions•5 pages•~75 min
Use this quiz track to strengthen recall, speed, and exam-style decision making. Attempt one page first, review explanations, and then re-attempt incorrect questions without notes.
A good scoring strategy is to mark uncertain questions, finish known ones quickly, and return with elimination logic. This improves accuracy while keeping momentum under time constraints.
Progress: 0 / 500%
Page 4 of 5 • Questions 31-40 of 50
Q31easy
What is the main purpose of the Accumulator register?
Q32medium
What is the main advantage of hardwired control over microprogrammed control?
Q33medium
What is the cache mapping where block number = (memory block number) mod (number of cache blocks)?
Q34medium
What is the main purpose of pipeline stalls (bubbles)?
Q35easy
What is the cache replacement policy that replaces oldest block?
Q36easy
What is the main purpose of the Status Register?
Q37medium
What is the main advantage of write-through cache?
Q38easy
What is the number of ways in a 4-way set-associative cache?
Q39medium
What is the main purpose of branch target buffer?
Q40easy
What is the cache miss penalty?
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