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GATE CS - Previous Year Questions

Previous-year GATE CS prompts for practice — options only until official keys are verified

142 questions15 pages~213 min

Practice with previous-year prompts and options. Official answer keys are not shown here yet — mark your choice, then verify against the IIT key PDF.

Use this track for exam reading speed and elimination practice until verified keys are linked.

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Page 10 of 15 • Questions 91-100 of 142

Practice mode: questions and options only. Official IIT answer keys are not linked here yet — mark your choice, then cross-check the official key yourself.

Q91medium

[GATE CS 2024 Set-1 Q28] Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

A)With no propagation delays, the output 𝒀 is always logic Zero

B)With no propagation delays, the output 𝒀 is always logic One With propagation delays, the output 𝒀 can have a transient logic One after 𝑿

C)transitions from logic Zero to logic One With propagation delays, the output 𝒀 can have a transient logic Zero after 𝑿

D)transitions from logic One to logic Zero Page 18 of 36 Organizing Institute: IISc Bengaluru Computer Science and Information Technology Set 1 (CS1)

Q92medium

[GATE CS 2024 Set-1 Q29] TCP client P successfully establishes a connection to TCP server Q. Let 𝑁 denote 𝑃 the sequence number in the SYN sent from P to Q. Let 𝑁 denote the 𝑄 acknowledgement number in the SYN ACK from Q to P. Which of the following statements is/are CORRECT?

A)The sequence number 𝑁 is chosen randomly by P 𝑃

B)The sequence number 𝑁 is always 0 for a new connection 𝑃

C)The acknowledgement number 𝑁 is equal to 𝑁 𝑄 𝑃

D)The acknowledgement number 𝑁 is equal to 𝑁 + 1 𝑄 𝑃

Q93medium

[GATE CS 2024 Set-1 Q30] Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT? In a pipelined execution, forwarding means the result from a source stage of an

A)earlier instruction is passed on to the destination stage of a later instruction In forwarding, data from the output of the MEM stage can be passed on to the

B)input of the EX stage of the next instruction

C)Forwarding cannot prevent all pipeline stalls Forwarding does not require any extra hardware to retrieve the data from the

D)pipeline stages Page 19 of 36 Organizing Institute: IISc Bengaluru Computer Science and Information Technology Set 1 (CS1)

Q94medium

[GATE CS 2024 Set-1 Q31] Which of the following fields is/are modified in the IP header of a packet going out of a network address translation (NAT) device from an internal network to an external network?

A)Source IP

B)Destination IP

C)Header Checksum

D)Total Length

Q95medium

[GATE CS 2024 Set-1 Q36] sends a file of size 106 bytes to R via this path by splitting the file into chunks of 103 bytes each. Node P sends these chunks one after the other without any wait time between the successive chunk transmissions. Assume that the size of extra headers added to these chunks is negligible, and that the chunk size is less than the MTU. Each of the links P—Q and Q—R has a bandwidth of 106 bits/sec, and negligible propagation latency. Router Q immediately transmits every packet it receives from P to R, with negligible processing and queueing delays. Router Q can simultaneously receive on link P—Q and transmit on link Q—R. Assume P starts transmitting the chunks at time 𝑡 = 0. Which one of the following options gives the time (in seconds, rounded off to 3 decimal pla...

A)8.000

B)8.008

C)15.992

D)16.000 Page 22 of 36 Organizing Institute: IISc Bengaluru Computer Science and Information Technology Set 1 (CS1)

Q96medium

[GATE CS 2024 Set-1 Q37] Consider the following syntax-directed definition (SDD). 𝑆 → 𝐷𝐻𝑇𝑈 { 𝑆.𝑣𝑎𝑙 = 𝐷.𝑣𝑎𝑙 + 𝐻.𝑣𝑎𝑙 + 𝑇.𝑣𝑎𝑙 + 𝑈.𝑣𝑎𝑙; } 𝐷 → "M"𝐷 { 𝐷.𝑣𝑎𝑙 = 5 + 𝐷 .𝑣𝑎𝑙; } 1 1 𝐷 → 𝜖 { 𝐷.𝑣𝑎𝑙 = −5; } 𝐻 → "L"𝐻 { 𝐻.𝑣𝑎𝑙 = 5∗10 + 𝐻 .𝑣𝑎𝑙; } 1 1 𝐻 → 𝜖 { 𝐻.𝑣𝑎𝑙 = −10; } 𝑇 → "C"𝑇 { 𝑇.𝑣𝑎𝑙 = 5∗100 + 𝑇 .𝑣𝑎𝑙; } 1 1 𝑇 → 𝜖 { 𝑇.𝑣𝑎𝑙 = −5; } 𝑈 → "K" { 𝑈.𝑣𝑎𝑙 = 5; } Given "MMLK" as the input, which one of the following options is the CORRECT value computed by the SDD (in the attribute 𝑆.𝑣𝑎𝑙)?

A)45

B)50

C)55

D)65 Page 23 of 36 Organizing Institute: IISc Bengaluru Computer Science and Information Technology Set 1 (CS1)

Q97medium

[GATE CS 2024 Set-1 Q38] Consider the following grammar 𝐺, with 𝑆 as the start symbol. The grammar 𝐺 has three incomplete productions denoted by (1), (2), and (3). 𝑆 → 𝑑𝑎𝑇 | (1) 𝑇 → 𝑎𝑆 | 𝑏𝑇 | (2) 𝑅 → (3) | 𝜖 The set of terminals is {𝑎,𝑏,𝑐,𝑑,𝑓}. The FIRST and FOLLOW sets of the different non-terminals are as follows. FIRST(𝑆) = {𝑐,𝑑,𝑓}, FIRST(𝑇) = {𝑎,𝑏,𝜖}, FIRST(𝑅) = {𝑐,𝜖} FOLLOW(𝑆) = FOLLOW(𝑇) = {𝑐,𝑓,$}, FOLLOW(𝑅) = {𝑓} Which one of the following options CORRECTLY fills in the incomplete productions?

A)(1) 𝑆 → 𝑅𝑓 (2) 𝑇 → 𝜖 (3) 𝑅 → 𝑐𝑇𝑅

B)(1) 𝑆 → 𝑓𝑅 (2) 𝑇 → 𝜖 (3) 𝑅 → 𝑐𝑇𝑅

C)(1) 𝑆 → 𝑓𝑅 (2) 𝑇 → 𝑐𝑇 (3) 𝑅 → 𝑐𝑅

D)(1) 𝑆 → 𝑅𝑓 (2) 𝑇 → 𝑐𝑇 (3) 𝑅 → 𝑐𝑅 Page 24 of 36 Organizing Institute: IISc Bengaluru Computer Science and Information Technology Set 1 (CS1)

Q98medium

[GATE CS 2024 Set-1 Q39] Consider the following pseudo-code. 𝐿1: 𝑡1 = −1 𝐿2: 𝑡2 = 0 𝐿3: 𝑡3 = 0 𝐿4: 𝑡4 = 4∗𝑡3 𝐿5: 𝑡5 = 4∗𝑡2 𝐿6: 𝑡6 = 𝑡5∗𝑀 𝐿7: 𝑡7 = 𝑡4+𝑡6 𝐿8: 𝑡8 = 𝑎[𝑡7] 𝐿9: if 𝑡8 <= 𝑚𝑎𝑥 goto 𝐿11 𝐿10: 𝑡1 = 𝑡8 𝐿11: 𝑡3 = 𝑡3+1 𝐿12: if 𝑡3 < 𝑀 goto 𝐿4 𝐿13: 𝑡2 = 𝑡2+1 𝐿14: if 𝑡2 < 𝑁 goto 𝐿3 𝐿15: 𝑚𝑎𝑥 = 𝑡1 Which one of the following options CORRECTLY specifies the number of basic blocks and the number of instructions in the largest basic block, respectively ?

A)6 and 6

B)6 and 7

C)7 and 7

D)7 and 6 Page 25 of 36 Organizing Institute: IISc Bengaluru Computer Science and Information Technology Set 1 (CS1)

Q99medium

[GATE CS 2024 Set-1 Q40] Consider the following two threads T1 and T2 that update two shared variables a and b. Assume that initially a = b = 1. Though context switching between threads can happen at any time, each statement of T1 or T2 is executed atomically without interruption. T1 T2 a = a + 1; b = 2 * b; b = b + 1; a = 2 * a; Which one of the following options lists all the possible combinations of values of a and b after both T1 and T2 finish execution?

A)(a = 4, b = 4); (a = 3, b = 3); (a = 4, b = 3)

B)(a = 3, b = 4); (a = 4, b = 3); (a = 3, b = 3)

C)(a = 4, b = 4); (a = 4, b = 3); (a = 3, b = 4)

D)(a = 2, b = 2); (a = 2, b = 3); (a = 3, b = 4)

Q100medium

[GATE CS 2024 Set-1 Q41] An array [82, 101, 90, 11, 111, 75, 33, 131, 44, 93] is heapified. Which one of the following options represents the first three elements in the heapified array?

A)82, 90, 101

B)82, 11, 93

C)131, 11, 93

D)131, 111, 90 Page 26 of 36 Organizing Institute: IISc Bengaluru Computer Science and Information Technology Set 1 (CS1)

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